1. Field of the Invention
This invention relates to an interconnect structure for integrated circuit devices and, more particularly, to a low-resistance aluminum-metal and silicon compound interconnect structure for connecting elements within an integrated circuit and to a method of manufacturing the interconnect structure.
2. Background of the Prior Art
Most integrated circuits are formed by active regions at the surface of a semiconductor substrate, typically, on monocrystalline silicon. These active regions are interconnected in part by conducting regions formed at the surface of the substrate. Other interconnecting lines are formed by the deposition of a conducting layer over an insulating layer covering the surface of the substrate. The conducting layer is delineated into interconnecting lines which contact the active regions of the substrate at preselected locations through holes in the insulating layer. Some integrated circuits have another insulating layer covering the interconnecting lines upon which a second set of interconnecting lines is formed. This second interconnecting layer contacts the interconnecting layer below through holes in the second insulating layer or may contact the substrate itself through holes in the first and second insulating layers.
Still more complex integrated circuits have more alternating layers of insulation and conducting material to form more sets of interconnecting lines. Generally, though, most complex integrated circuits have two sets of interconnecting lines, a top layer and an intermediate layer.
These interconnecting lines form the interconnect structure by which the elements, active and passive, of the integrated circuit are electrically coupled for the functioning of the circuit.
In present integrated circuits, the top conducting layer is usually formed from aluminum. The intermediate conducting layer or layers below the top conducting layer are formed from aluminum or polysilicon. Another material which has been examined as a possible candidate for intermediate conducting layers is some refractory metal silicide. All of these materials have various shortcomings.
Refractory metal silicides and polysilicon have the same general shortcomings as intermediate conducting layers. These materials, for example, have high sheet resistances compared with aluminum. Polysilicon sheet resistance is usually equal to or greater than fifteen ohms per square and silicides have sheet resistances usually equal to or greater than three ohms per square. Such high sheet resistances slow down the speed of integrated circuits. Secondly, these materials typically form high resistance or nonohmic contacts with either or both N+ or P+ regions in the substrate of the semiconductor substrate. In CMOS technology both N+ and P+ regions must contact the conducting lines. Polysilicon and refractory metal silicide interconnecting lines are particularly troublesome because the P or N doping of the interconnecting lines will create a P-N junction with an oppositely doped contact substrate region normally found in a CMOS layout.
A metal silicide or polysilicon interconnecting line must completely cover the contact region to the substrate, sometimes called "dog boning". The complete overlapping of the contact area by the silicide or polysilicon interconnecting line prevents the silicon substrate surface from gouging because etchants for polysilicon and silicides typically will also etch silicon. Gouging of the substrate silicon is avoided by "dog boning" the interconnecting layer to completely cover the contact region, even with the occurrence of masking misalignments. However, this reduces the density of the integrated circuit. See FIG. 2 which illustrates an interconnection line 20 having "dog bone" contacts and a line 21 which does not. It is easy to see that a set of interconnecting lines having "dog bone" contacts could be less tightly integrated compared to interconnecting lines of the same width W.
Another disadvantageous requirement for refractory metal silicide and polysilicon interconnecting lines is that of high temperature annealing. Any high temperature annealing step, normally at or above 900.degree. C., will cause the junction depths of the doped regions of the silicon substrate to diffuse deeper. This increases the parasitic capacitances in the integrated circuit which ultimately reduces its speed.
Another material which has been used in the prior art for an intermediate interconnect layer to avoid the problems above is aluminum. Aluminum has the disadvantage of having bumps on its surface which cause the insulating layer placed over the aluminum to have hillocks. These hillocks, or irregularities, may cause interdielectric short circuits between the intermediate conducting layer and the conducting layer above.
Aluminum also does not provide adequate step coverage in many applications. For example, when aluminum is deposited on the insulating layer covering the substrate, it will not deposit evenly on the sides of a contact opening to the substrate. Rather, the aluminum tends to accumulate in certain places and avoid other places, thereby increasing the likelihood of open circuits in the interconnecting lines formed.
Furthermore, since present day production technology has not yet produced a totally satisfactory plasma etch for aluminum, wet etching is still widely used. Wet etching results in a large masking pitch between neighboring aluminum interconnect lines. This reduces the overall density of the integrated circuit.
Another disadvantage of aluminum is that the material when in contact with silicon, readily absorbs silicon to form an aluminum-silicon compound. This increases the possibility of aluminum spiking into the substrate through shallow P-N junctions used in present day MOS VLSI integrated circuits to cause short circuits.
Still another disadvantage of an intermediate aluminum interconnect layer is that it does not permit the reworking of the top aluminum layer when mistakes in photolithography occur. Since both materials are aluminum, the task of removing the top layer without affecting the intermediate interconnect layer becomes very difficult, if not impossible. An etch of the top layer will invariably remove part of the intermediate layer where contact is made between the two layers.
Finally, since both interconnection layers are aluminum, the top layer is required to have a "dog bone" contact to the lower aluminum layer. Otherwise, the exposed open contact area of the lower aluminum layer will be etched when the top layer is defined into interconnecting lines. As mentioned previously, this increases the masking pitch of the top aluminum layer and reduces the overall density of the integrated circuit.
The present invention overcomes or substantially mitigates these semiconductor process, structural and electrical shortcomings.